# Results for: “Saradindu Panda”

2 eBooks

## CH6-1 |
Saradindu Panda | Laxmi Publications | |||||

Chapter 6 � SEQUENTIAL LOGIC CIRCUIT DESIGN 6.1 INTRODUCTION If we neglect the propagation delay time, the output of the combinational logic circuit, at any given time point are directly determined as Boolean function of the input variables applied at that time. Thus, the combinational circuits lack of the capability of storing any previous events, or displaying an output behaviour which is dependent upon the previously applied inputs. The sequential circuit gives the output, which is determined by the current inputs as well as the previously applied input variables. Bistable circuits have, as their name implies, two stable stages or operation modes, each of which can be attained under certain input and output condition. Monostable circuits, have only one stable operating point (state). All basic Latch and flip-flop circuits, registers and memory elements used in digital systems fall into this category. 6.2 BEHAVIOUR OF BI-STABLE ELEMENTS The basics of a bi-stable elements is that, it has two identical cross-coupled inverter circuits, as shown in figure given below: See All Chapters |
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## CH5-1 |
Saradindu Panda | Laxmi Publications | |||||

Chapter 5 � DYNAMIC VLSI DESIGN 5.1 INTRODUCTION In the static CMOS logic with a fan-in of N requires 2N devices. A variety of approaches were presented to reduce the number of transistors required to implement a given logic function including pseudo-nMOS, pass-transistor logic. etc. For the pseudo, nMOS logic, there are (N + 1) no of transistor required to implement an N input logic gate, but it has static power dissipation. To avoid this static power dissipation and obtaining the same result, the alternating approach is called the dynamic logic design. With the addition of a clock input, it uses a sequence of precharge and conditional evaluation phase. There are different style to design a dynamic VLSI circuits: (i) Precharge evaluation logic style. (ii) Dynamic TG logic style. (iii) Pass transistor logic style. (iv) Domino logic style. (v) NORA logic style. 5.2 PRE-CHARGE AND EVALUATION LOGIC STYLE The operation of this circuit is divided into two major phases — pre-charge and evaluation — with the mode of operation determined by the clk signal clk. The basic construction of this type of design style is given below. See All Chapters |
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## ch9-2 |
Saradindu Panda | Laxmi Publications | |||||

144 ANALOG AND DIGITAL VLSI CIRCUIT DESIGN 2ID1 2ID2 ∴ vin1 – vin2 = (vgs1 = vgs2) = or, (vin1 – vin2)2 = or, 1 W K′ (vin1 – vin2)2 – ISS = – 2 ID1 ID2 2 L or, 4ID1ID2 = (ID1 + ID2)2 – (ID1 – ID2)2 or, K′ – W L K′ (when, VT1 = VT2 = VT) W L 2 (I – 2 ID1 ID2 ) W SS K′ L (... ID1 + ID2 = ISS) ...(1) 4ID1ID2 = ISS2 – (ID1 – ID2)2 ...(2) Again, from equation (1), 2 4ID1ID2 = ISS2 + W 1 1 W 4 I (v – vin2)2 K ′ L (vin1 – vin2) – 2. K′ 4 2 L SS in1 Equating equation (2) and equation (3), we get, 2 K′W K′ W ISS2 – (ID1 – ID2)2 = ISS2 + (vin1 – vin2)4 – ISS (vin1 – vin2) L 2 L or, 1 (ID1 + ID2) = – 4 Thus, (ID1 + ID2)2 = 2 2 W K ′ W 4 2 K ′ L (vin1 – vin2) + ISS (vin1 – vin2) . L 1 W µ c (vin1 – vin2) 2 n ox L 4ISS µ n cox where K′ = µn cox. If, vin1 = vin2 then ID1 – ID2 = 0 or ID1 = ID2. W L − (vin1 – v in2 ) 2 As |vin1 – vin2| increases from zero, then |ID1 – ID2| also increases. * ∴ Gm = δ(∆ID ) 1 W = µn cox 2 L δ(∆Vin ) For, ∆Vin = 0, Since, ∴ Gm = µn cox 4ISS 2 − 2∆Vin µn cox W/L 4ISS 2 − ∆Vin µ n cox W/L W I L SS Vout1 – Vout2 = ∆I . RD = RD Gm . ∆vin Av = µn cox See All Chapters |
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## ch10-1 |
Saradindu Panda | Laxmi Publications | |||||

154 ANALOG AND DIGITAL VLSI CIRCUIT DESIGN 10.2 SWITCHED CAPACITOR INTEGRATOR A : Continuous Time Integrator : Very important component of filters and over sampled A/D converters, is the continuous time integrator. Figure 10.3 shows the circuit. The output is, Vout = – 1 R cf |Vin dt ...(4) Fig. 10.3 (if the output Amp. gain is very large). For sampled data system, we need a discrete-time counterpart of this circuit. B : Discrete Time Integrator : Here, we replace r by a switched capacitor. Fig. 10.4. Response to a constant input voltage Z1 = 1 1 . Z2 = j ωc1 j ωc2 Vout = – Z2 jωc1 1 V =– . Vin = – Z1 in 1 jωc2 c1 c2 Vin Operation : In every clk pulse, (1) When S1 is ‘ON’ ; c1 absorbs a charge c1 Vin. (2) When S2 is ‘ON’ Deposite this charge on c2. (... Op-Amp. input does not draw any current). c1 Therefore, if Vin is constant, the output changes by Vin/clock cycle. c2 The output waveform is a staircase function. If we can approximate this staircase by a ramp, we get an integrator [c2 must be large capacitor.] The output at the end of the kth clock cycle is, See All Chapters |
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## CH7-1 |
Saradindu Panda | Laxmi Publications | |||||

Chapter 7 ARITHMETIC SUBSYSTEM 7.1 CARRY LOOKAHEAD ADDER The linear growth of adder carry delay with the size of the input word may be improved by calculating the carries to each stage in parallel. The carry of the ith stage, Ci may be expressed as, Ci = Gi + Pi . Ci – 1 where ...(i) Gi = Ai . Bi generate signal Pi = Ai ⊕ Bi propagate signal ...(ii) ...(iii) Expanding this, we get, Ci = Gi + Pi Gi – 1 + Pi Pi – 1 Gi – 2 + ....... + Pi Pi – 1 ...... P1 C0 ...(iv) The sum Si is generated by Si = Ci – 1 ⊕ Ai ⊕ Bi if ...(v) Pi = Ai ⊕ Bi For four stages of lookahead, the appropriate terms are C1 = G1 + P1C0 C2 = G2 + P2G1 + P2P1C0 C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0 C4 = G4 + P4G3 + P4P3G2 + P4P3P2G1 + P4P3P2P1C0 = G4 + P4 [G3 + P3{G2 + P2(G1 + P1C0)}] ...(vi) A possible implementation of the carry gate for this kind of carry lookahead adder for 4 bits is shown in Fig. 7.1(a). Note that the gates have been partitioning to keep the number of inputs less than or equal to four. This is typical of the type of carry lookahead that would be used in a gate array or standard cell design. See All Chapters |