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6

Optoelectronic

Devices

6.1

INTRODUCTION

Optoelectronics deals with the interaction of electronic processes with light and optical processes. Devices in which such interaction can suitably take place, usually accompanied by an energy conversion process (e.g., from electrical to optical, and vice versa), are called optoelectronic devices. Such devices are conveniently made by the semiconductors.

6.2

PHOTODIODES

Photodiodes and crystalline solar cells are essentially the same as the p-n diodes, which have been described in this chapter. However, the diode is exposed to light, which yields a photocurrent in addition to the diode current so that the total diode current is given by:

e

j

I = Is e Va / Vt - 1 - I ph

... (6.1)

where the additional photocurrent, Iph, is due to photogeneration of electrons and holes shown in Fig. 6.1. These electrons and holes are pulled into the region where they are majority carriers by the electric field in the depletion region. hn

depletion region

hole electron

+

Va

n-type substrate

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Chapter

4

STATIC VLSI DESIGN

4.1 INTRODUCTION

There are numerous circuit styles to implement a given logic function. As with the inverter, the common design metrics by which a gate is evaluated are area, speed, energy and power.

Depending on the application, the emphasis will be on different metrics, by which a gate is evaluated. For example, the switching speed of digital circuits is the primary metric in a high performance processor, while in a battery operated circuit, it is energy dissipation.

Recently, power dissipation also has become an important concern and considerable emphasis is placed on understanding the sources of power and approaches to dealing with power. In addition to there metrics, roburtness to noise and reliability are also very important considerations.

The complementary CMOS circuit style falls under a broad class of logic circuits called static circuits in which at every point in time, each gate output is connected to either VDD or VSS via a low resistance path.

There are different static design procedure exist in VLSI circuit design technology:

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ANALOG

AND

DIGITAL VLSI CIRCUIT DESIGN

Poly contact (CCP)

Active contact (CCA)

5.1(a)

exact contact size

2×2

5.2(a)

minimum poly overlap

1.5

5.3(a)

minimum contact spacing

2

6.1(a)

exact contact size

2×2

6.2(a)

minimum active overlap

1.5

6.3(a)

minimum contact spacing

2

6.4(a)

minimum space to gate of transistor

2

1. To ensure source and drain width.

2. Different select types may touch but not overlap.

• MOSIS Scalable CMOS rules — Process back end:

Layer

Rule

Explanation

Value/λ

λ

Metal 1 (CMF)

7.1

minimum width

3

7.2(a)

minimum space

3

7.2(b)

minimum space (for minimum-width wires

Via 1 (CVA)

Metal 2 (CMS)

Via 2 (CVS)

Metal 3 (CMT)

only)

2

7.3

minimum overlap of poly contact

1

7.4

minimum overlap of active contact

1

8.1

exact size

2×2

8.2

minimum via spacing

3

8.3

minimum overlap by metal 1

1

8.4

minimum spacing to contact

2

8.5

minimum spacing to poly or active edge

2

9.1

minimum width

3

9.2(a)

minimum space

4

9.2(b)

minimum space (for minimum-width wires only)

3

9.3

minimum overlap of via 1

1

14.1

exact size

2×2

14.2

minimum spacing

3

14.3

minimum overlap by metal 2

1

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168

Microelectronics and Optoelectronics Technology

Now,

The axial strain

\

= ea ea =

FG DL IJ

HL K

... (7.1)

0

Stress = s s=

F

=

Area

F

F DI pG J

H 2K

2

... (7.2)

Strain is a dimensionless quantity, and is usually expressed in units of 10–6 or microstrains, because for most materials strain values are quite small.

The units of stress s are commonly N/m2 or Pa.

The standard sign convention for stress is for tensile stresses to be negative and compressive stresses to be negative and compressive stresses to be positive.

Here the force F, in figure is acting perpendicularly to the end of the rod. This type of force is termed an axial force, and results in an axial strain ea and axial stress ¶a.

Shear forces, which act parallel to the surface of a body, generate shear stress and strain. From the Hooke’s law we get, where

¶ = eE

E = slope of the stress-strain curve.

... (7.3)

Another important mechanical effect is the change in lateral dimensions due to an axial force.

The rod in Fig. 1 is shown as decreasing in diameter as a result of the axial tensile force F. This change in width is characterised by a lateral strain ec, which is related to the axial strain ea by Poisson’s ratio v by, v =–

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Index

A

A Carry Lookahead Adder 162

Actel Routing Methodology 15

Active Area Definition 21

Active Load Inverter 43

Altera Routing Methodology 16

Annealing 24

Antifuse Technology 10

B

Basic n-well CMOS Process 25

Behaviour of Bi-stable Elements 74

Bipolar Rom 94

Bisection Min-Cut 127

C

Cache Memory 97

Carry Lookahead Adder 83

Carry Lookahead Method 163

Channel-stop Implant 21

Circuit Description 102

Circuit Partitioning 116

Clock Planning 114

Clocked S-R Latch 79

Clusters 125

CMOS D-Latch 80

CMOS Dynamic TG Logic 67

CMOS Fabrication Sequence 20

Cmos Inverter 47

CMOS Inverter Designs 35

Complementary Pass Transistor Logic

Style 60

Complete Graph 131

Complex Programmable Logic Device

(CPLD) 7

Contact Cuts 24

Coping with Hypergraph 122

Current Mirror 140

Current Sink and Current Source 138

Current Source 139

D

3T-DRAM 91

DCVSL Logic Gate 64

Depletion Load Logic Style 58

Design Constraints 103

Design Entry 13

Design Flow in ASIC 5

Design Planning 105

Design Synthesis 13

Detail Placement 128

Detail Routing 133

Differential Amplifier 142

Drawbacks of the Kernighan-Lin Heuristic

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