29 Chapters
Medium 9789351382492

ch9-2

Saradindu Panda Laxmi Publications PDF

144

ANALOG

AND

DIGITAL VLSI CIRCUIT DESIGN

2ID1

2ID2

vin1 – vin2 = (vgs1 = vgs2) =

or,

(vin1 – vin2)2 =

or,

1

W

K′

(vin1 – vin2)2 – ISS = – 2 ID1 ID2

2

L

or,

4ID1ID2 = (ID1 + ID2)2 – (ID1 – ID2)2

or,

K′

W

L

K′

(when, VT1 = VT2 = VT)

W

L

2

(I – 2 ID1 ID2 )

W SS

K′

L

(...

ID1 + ID2 = ISS)

...(1)

4ID1ID2 = ISS2 – (ID1 – ID2)2

...(2)

Again, from equation (1),

2

4ID1ID2 = ISS2 +

W

1 

1

W

4

I (v – vin2)2

 K ′ L  (vin1 – vin2) – 2. K′

4 

2

L SS in1

Equating equation (2) and equation (3), we get,

2

K′W

 K′ W 

ISS2 – (ID1 – ID2)2 = ISS2 + 

(vin1 – vin2)4 –

ISS (vin1 – vin2)

L

 2 L

or,

1

(ID1 + ID2) = –

4

Thus,

(ID1 + ID2)2 =

2

2

W

 K ′ W

4

2

 K ′ L  (vin1 – vin2) + ISS 

 (vin1 – vin2) .

 L 

1

W

µ c

(vin1 – vin2)

2 n ox L

4ISS

µ n cox

where K′ = µn cox.

If, vin1 = vin2 then ID1 – ID2 = 0 or ID1 = ID2.

W

L

− (vin1 – v in2 ) 2

As |vin1 – vin2| increases from zero, then |ID1 – ID2| also increases.

* ∴ Gm =

δ(∆ID )

1

W

=

µn cox

2

L

δ(∆Vin )

For, ∆Vin = 0,

Since,

Gm =

µn cox

4ISS

2

− 2∆Vin

µn cox W/L

4ISS

2

− ∆Vin

µ n cox W/L

W

I

L SS

Vout1 – Vout2 = ∆I . RD = RD Gm . ∆vin

Av =

µn cox

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Medium 9789351382492

CH8-3

Saradindu Panda Laxmi Publications PDF

120

ANALOG

AND

DIGITAL VLSI CIRCUIT DESIGN

• D′′x = D′x + 2cxp – 2cxq, ∀ x ∈ A – {p}

D′′a = D′a + 2cac – 2cae = 0 + 2 × 2 – 2 × 2 = 0

D′′d = D′d + 2cde – 2cdc = 1 + 2 × 4 – 2 × 3 = 3

• gxy = D′′x + D′′y – 2cxy

g3 = – 3) gad = D′′a + D′′d – 2cad = 0 + 3 – 2 × 3 = – 3 ( ¶ n gi = 0 ).

• Note that this step is redundant ( ∑ i = 1 µ

¶ = g = – 3. g1 = gbf = 4, ¶ g2 = gce = – 1, g

• Summary ¶

3 ad

• Largest partial sum max

k

∑i=1

µ gi = 4 (k = 1)

⇒ Swap b and f.

Weighted Example (cont’d) a b c d e f

a

b

c

d

e

f

0

1

2

3

2

4

1

0

1

4

2

1

2

1

0

3

2

1

3

4

3

0

4

3

2

2

2

4

0

2

4

1

1

3

2

0

Initial cut cost = (1 + 3 + 2) + (1 + 3 + 2) + (1 + 3 + 2) = 18(22 – 4)

• Iteration 2 : Repeat what we did at Iteration 1 (Initial cost = 22 – 4 = 18).

¶ = g = 4. g1 = gce = – 1, ¶ g2 = gab = – 3, g

• Summary : ¶

3 fd

• Largest partial sum = max

∑i=1 k

µ gi = 0 (k = 3)

⇒ Stop !

Algorithm : Kernighan-Lin (G)

Input : G = (V, E), | V | = 2n.

Output : Balanced bi-partition A and B with “small” cut cost.

1. begin

2. Bipartition G into A and B such that | VA | = | VB |, VA ∩ VB = φ, and VA ∪ VB = V.

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Medium 9788131807385

Ch_2

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2

Carrier Transport

2.1

INTRODUCTION

Any motion of free carriers in a semiconductor leads to a current. This motion can be caused by an electric field due to an externally applied voltage, since the carriers are charged particles. We will refer to this transport mechanism as carrier drift. In addition, carriers also move from regions where the carrier density is high to regions where the carrier density is low. This carrier transport mechanism is due to the thermal energy and the associated random motion of the carriers. We will refer to this transport mechanism as carrier diffusion. The total current in a semiconductor equals the sum of the drift and the diffusion current.

As one applies an electric field to a semiconductor, the electrostatic force causes the carriers to first accelerate and then reach a constant average velocity, v, due to collisions with impurities and lattice vibrations. The ratio of the velocity to the applied field is called the mobility. The velocity saturates at high electric fields reaching the saturation velocity. Additional scattering occurs when carriers flow at the surface of a semiconductor, resulting in a lower mobility due to surface or interface scattering mechanisms.

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Medium 9789351382492

CH7-1

Saradindu Panda Laxmi Publications PDF

Chapter

7

ARITHMETIC SUBSYSTEM

7.1 CARRY LOOKAHEAD ADDER

The linear growth of adder carry delay with the size of the input word may be improved by calculating the carries to each stage in parallel.

The carry of the ith stage, Ci may be expressed as,

Ci = Gi + Pi . Ci – 1 where

...(i)

Gi = Ai . Bi

generate signal

Pi = Ai ⊕ Bi

propagate signal

...(ii)

...(iii)

Expanding this, we get,

Ci = Gi + Pi Gi – 1 + Pi Pi – 1 Gi – 2 + ....... + Pi Pi – 1 ...... P1 C0

...(iv)

The sum Si is generated by

Si = Ci – 1 ⊕ Ai ⊕ Bi if

...(v)

Pi = Ai ⊕ Bi

For four stages of lookahead, the appropriate terms are

C1 = G1 + P1C0

C2 = G2 + P2G1 + P2P1C0

C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0

C4 = G4 + P4G3 + P4P3G2 + P4P3P2G1 + P4P3P2P1C0

= G4 + P4 [G3 + P3{G2 + P2(G1 + P1C0)}]

...(vi)

A possible implementation of the carry gate for this kind of carry lookahead adder for

4 bits is shown in Fig. 7.1(a). Note that the gates have been partitioning to keep the number of inputs less than or equal to four. This is typical of the type of carry lookahead that would be used in a gate array or standard cell design.

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Ch_4

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4

MOS Capacitors

4.1

INTRODUCTION

The primary reason to study the Metal-Oxide-Silicon (MOS) capacitor is to understand the principle of operation as well as the detailed analysis of the Metal-Oxide-Silicon Field

Effect Transistor (MOSFET). In this chapter, we introduce the MOS structure and its four different modes of operation, namely accumulation, flatband, depletion and inversion. We then consider the flatband voltage in more detail and present the MOS analysis based on the full depletion approximation. Finally, we analyze and discuss the MOS capacitance.

4.2

STRUCTURE AND PRINCIPLE OF OPERATION

The MOS capacitor consists of a Metal-Oxide-Semiconductor structure as illustrated by

Fig. 4.1. Shown in the semiconductor substrate with a thin oxide layer and a top metal contact, referred to as the gate. A second metal layer forms an Ohmic contact to the back of the semiconductor and is called the bulk contact. The structure shown has a p-type substrate. We will refer to this as an n-type MOS or nMOS capacitor since the inversion layer—as discussed in section 4.6.4—contains electrons. nMOS : Metal-Oxide-Semiconductor

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