116 Slices
Medium 9781601323262

A Safety Information Sharing Application on BBISS

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

490

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

A Safety Information Sharing Application on BBISS

Tomomi Itoh1, Ayami Manaka1, Yuuka Sugawara1,

Hiroshi Ishii1, Hiroaki Nishikawa2, and Keisuke Utsu1

1

School of Information and Telecommunication Engineering, Tokai University, Minato, Tokyo, Japan

2

Graduate School of Systems and Information Engineering, University of Tsukuba, Tsukuba, Ibaraki, Japan

Abstract – Large-scale disasters frequently happen in Japan.

People in disaster areas may try to send and get safety information of themselves, their family or friends. However, since communication infrastructure including servers are often unavailable in the situations, it may be difficult for the people to share the information using the infrastructure. To solve this problem, we have proposed Broadcast Based

Information Sharing System, BBISS, which can communicate in peer-to-peer (P2P) manner without servers and the communication infrastructures. On the top of BBISS, we develop a safety information sharing application to actually enable users to utilize the service. The paper reports the prototype design and the implementation of the application and future study issues.

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Medium 9781601323262

A Novel Method to Minimize Side Effects by Cache Contention on the Inclusive Multi-Core Shared Cache

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

A Novel Method to Minimize Side Effects by Cache

Contention on the Inclusive Multi-Core Shared Cache

Hyo-Joong Suh1

School of Computer Science and Information Engineering,

The Catholic University of Korea, Bucheon-si, Gyeonggi-do, Korea

1

Abstract - Cache contention is annoying issue of the multicore processors with private L1 cache and inclusive shared L2 cache. If core P1 runs with small working set which fits in its

L1 cache while core P2 runs cache consuming process, loaded blocks in the shared L2 cache by P1 are extinguished by frequent access from P2. Furthermore, it incurs an inevitable invalidate to the L1 cache of the core P1 by the multi-level cache inclusion property. This study focused on this problem, and solves by access grouping with extension of cache status. Simulation results show the proposed method minimizes the side effects by the cache contention on the inclusive shared cache.

workloads are dispatched on the each core with shared L2 cache, lightweight core is disturbed by invalidation requests to maintain the inclusion property between caches. Fig. 2 shows the cache contention [2] and invalidation by inclusion which this study addressed to resolve.

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Medium 9781601323262

Enhanced Automated Data Dependency Analysis for Functionally Correct Parallel Code

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

312

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

Enhanced Automated Data Dependency Analysis for Functionally

Correct Parallel Code

Prasad Pawar1 , Pramit Mehta1 , Naveen Boggarapu1 , and Léo Grange1

1 Center for Research of Engineering Sciences and Technology (CREST), KPIT Technologies Ltd., Pune, India

Abstract— There is a growing interest in the migration of legacy sequential applications to multicore hardware while ensuring functional correctness powered by automatic parallelization tools. OpenMP eases the loop parallelization process, but the functional correctness of parallelized code is not ensured. We present a methodology to automatically analyze and prepare OpenMP constructs for automatic parallelization, guaranteeing functional correctness while benefiting from multicore hardware capabilities. We also present a framework for procedural analysis, and emphasize the implementation aspects of this methodology. Additionally, we cover some of the imperative enhancements to existing dependency analysis tests, like handling of unknown loop bounds. This method was used to parallelize an Advance Driver Assistance System (ADAS) module for Lane

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Medium 9781601323262

Accelerating Medical Image Registration Using a SIMD Array

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

28

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

Accelerating Medical Image Registration Using a SIMD

Array

I. K. Jeong1, M. S. Kang1, C. H. Kim2 and J. M. Kim1,*

School of Electrical Engineering, University of Ulsan, Ulsan, South Korea

2

School of Electronics and Computer Engineering, Chonnam National University, Gwangju, South Korea

1

Abstract - Medical image registration plays an important role in medical imaging in the early detection of cancers. An essential component in most medical registration approaches is resampling algorithms. These algorithms, however, demand tremendous computational power associated with similarity computation. The increasing availability of parallel computers makes parallelizing these tasks an attractive option. This paper presents parallel approaches for the resampling algorithms using a representative parallel Single Instruction,

Multiple Data (SIMD) processor array to meet the computational requirements. This paper also presents not only a general theory of resampling algorithms including rotation, scaling, and translation, but also parallel implementations of these algorithms on the SIMD processor array. Experimental results show that parallel approaches achieve a speedup of

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Medium 9781601323262

Spatial Parallelization of Self-Timed FFT Circuit

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

521

Spatial Parallelization of Self-Timed FFT Circuit

Norifumi UNO, Ryuichi TAGUCHI, and Makoto IWATA

Graduate School of Engineering, Kochi University of Technology,

Kami, Kochi, 782-8502 Japan

and multichannel, FFT, self-timed pipeline, spatial parallelization

communication condition. This sort of seamless handover in

DWS will also contribute to energy efficiency.

There have been many studies on high-speed FFT circuits

[6], [7], [8], [9] which can be applied to 2.4 G sample/s wireless personal area network (WPAN) standard. Flexible-radixconfiguration multipath-delay-feedback (FRCMDF) FFT circuit [6] supports triple modes for WPAN, wireless local area network (WLAN), and mobile broadband wireless access

(MBWA) applications. However, this circuit operates only in a single mode at the same time. Therefore, a basic architecture of multimode and multichannel FFT (MM-FFT) circuit based on the STP circuit was proposed in [7], its performance could not reach to 2.4 G sample/s required for

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