116 Slices
Medium 9781601323262

Parallel Fuzzy Filter for Impulse Noise Removal

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

57

Parallel Fuzzy Filter for Impulse Noise Removal

J. Arnal1 , L. A. Drummond2 , L. B. Súcar1 , and V. Vidal3

1 Departamento de Ciencia de la Computación e Inteligencia Artificial,

Universidad de Alicante, San Vicente del Raspeig, Alicante, Spain

2 Lawrence Berkeley National Laboratory, Berkeley, CA, USA

3 Departamento de Sistemas Informáticos y Computación,

Universidad Politécnica de Valencia, Grao de Gandia, Valencia, Spain

Abstract— A parallel algorithm for reducing impulse noise from color images is proposed. The algorithm is based on a fuzzy metric and is performed in two steps followed by noise

filtering using the vector median filter. An implementation of the algorithm on multi-core interface using the Open MultiProcessing (OpenMP) is presented. A performance analysis with large images is conducted. Performance is evaluated in terms of execution time and in terms of PSNR. Results show that the proposed filter obtains good performance in terms of

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Medium 9781601323262

Spatial Parallelization of Self-Timed FFT Circuit

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

521

Spatial Parallelization of Self-Timed FFT Circuit

Norifumi UNO, Ryuichi TAGUCHI, and Makoto IWATA

Graduate School of Engineering, Kochi University of Technology,

Kami, Kochi, 782-8502 Japan

and multichannel, FFT, self-timed pipeline, spatial parallelization

communication condition. This sort of seamless handover in

DWS will also contribute to energy efficiency.

There have been many studies on high-speed FFT circuits

[6], [7], [8], [9] which can be applied to 2.4 G sample/s wireless personal area network (WPAN) standard. Flexible-radixconfiguration multipath-delay-feedback (FRCMDF) FFT circuit [6] supports triple modes for WPAN, wireless local area network (WLAN), and mobile broadband wireless access

(MBWA) applications. However, this circuit operates only in a single mode at the same time. Therefore, a basic architecture of multimode and multichannel FFT (MM-FFT) circuit based on the STP circuit was proposed in [7], its performance could not reach to 2.4 G sample/s required for

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Medium 9781601323262

Task Scheduling Algorithm for Multicore Processor Systems with Turbo Boost and Hyper-Threading

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

229

Task Scheduling Algorithm for

Multicore Processor Systems with Turbo Boost and Hyper-Threading

Yosuke Wakisaka, Naoki Shibata, Keiichi Yasumoto, Minoru Ito

Nara Institute of Science and Technology

Nara, Japan

{yosuke-w, n-sibata, yasumoto, ito}@is.naist.jp

Abstract—In this paper, we propose a task scheduling algorithm for multiprocessor systems with Turbo Boost and HyperThreading technologies. The proposed algorithm minimizes the total computation time taking account of dynamic changes of the processing speed by the two technologies, in addition to the network contention among the processors. We constructed a clock speed model with which the changes of processing speed with Turbo Boost and Hyper-threading can be estimated for various processor usage patterns. We then constructed a new scheduling algorithm that minimizes the total execution time of a task graph considering network contention and the two technologies. We evaluated the proposed algorithm by simulations and experiments with a multi-processor system consisting of 4 PCs. In the experiment, the proposed algorithm produced a schedule that reduces the total execution time by

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Medium 9781601323262

Accelaration of Poisson Corrupted Image Restoration with Loopy Belief Propagation

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

165

Accelaration of Poisson Corrupted Image Restoration with Loopy

Belief Propagation

1

Hayaru SHOUNO1

Graduate School of Informatics and Engineering, University of Electro-Communications,

Chofugaoka 1-5-1, Chofu, JAPAN

Abstract— We treat acceleration of an image restoration throughout Poisson noise channels. Previously, we proposed a image restoration method by use of Expectation Maximization (EM) algorithm[1]. The method requires calculation of inverse of the accuracy matrix, which requires O(M 3 ) computational cost where M stands for the number of pixels, in order to obtain the posterior mean of some statistics value in each iteration. For reducing the calculation cost, we apply “loopy belief propagation(LBP)” algorithm into our method for the calculation of the marginal posterior means to substitute the posterior mean required in the EM algorithm. As the result, we can accelerate the previous algorithm over 10 times faster in the 80 × 80 size image.

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Medium 9781601323262

Modeling the Effects on Power and Performance from Memory Interference of Co-located Applications in Multicore Systems

Hamid R. Arabnia, Lou D'Alotto, Hiroshi Ishii, Minoru Ito, Kazuki Joe, Hiroaki Nishikawa, Georgios Sirakoulis, William Spataro, Giuseppe A. Trunfio, George A. Gravvanis, George Jandieri, Ashu M. G. Solo, Fernando G. Tinetti CSREA Press PDF

Int'l Conf. Par. and Dist. Proc. Tech. and Appl. | PDPTA'14 |

3

Modeling the Effects on Power and Performance from Memory Interference of

Co-located Applications in Multicore Systems

Daniel Dauwe1 , Ryan Friese1 ,

Sudeep Pasricha1,2 , Anthony A. Maciejewski1 , Gregory A. Koenig3 , and Howard Jay Siegel1,2

1

Department of Electrical and Computer Engineering

2

Department of Computer Science

Colorado State University

Fort Collins, CO, 80523

3

Oak Ridge National Laboratory

Oak Ridge, TN 37830

Abstract— In this study, we analyze interference trends when corunning multiple applications possessing varying degrees of memory intensity on multi-core processors. We conduct tests with PARSEC benchmark applications and explore energy consumption, execution times, and main memory accesses when interfering applications share last-level cache. We also explore how co-running applications are impacted when the processor frequency is modified using dynamic voltage and frequency scaling (DVFS). A portable and lightweight testing framework is presented and results are shown for experiments conducted on an Intel i7 quad-core system. It is shown that the degree of degradation due to co-location interference on execution time is highly dependent on the types and number of applications co-located on cores that share the last-level cache.

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