16 Slices
Medium 9781601322623

Session - Best Young Entrepreneur; Student Research Category

Toomas P. Plaks CSREA Press PDF
Medium 9781601322623

Heterogeneous Multicore Platform with Accelerator Templates and Its Implementation on an FPGA with Hard-core CPUs

Toomas P. Plaks CSREA Press PDF

Int'l Conf. Reconfigurable Systems and Algorithms | ERSA'13 |

47

Heterogeneous Multicore Platform with Accelerator Templates and

Its Implementation on an FPGA with Hard-core CPUs

Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama and Michitaka Kameyama

Graduate School of Information Sciences, Tohoku University

Aoba 6-6-05, Aramaki, Aoba, Sendai, Miyagi, 980-8579, Japan

Email: {takei, hasitha, hariyama, kameyama}@ecei.tohoku.ac.jp

Abstract— Heterogeneous multi-core architectures with

CPUs and accelerators attract many attentions since they can achieve power-efficient computing in various areas from low-power embedded processing to high-performance computing. Since the optimal architecture is different from application to application, finding the most suitable accelerator is very important. In this paper, we propose an FPGA-based heterogeneous multi-core platform with custom accelerator templates. Accelerator templates can be reused after optimizing for different applications. According to the evaluation, the proposed platform gives comparable performance to the industrial heterogeneous multicore processors at around 1W of power.

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Medium 9781601322623

An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core

Toomas P. Plaks CSREA Press PDF

36

Int'l Conf. Reconfigurable Systems and Algorithms | ERSA'13 |

An Automatic Design and Implementation Framework for

Reconfigurable Logic IP Core

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi

Graduate School of Science and Technology, Kumamoto University

Abstract— Conventional full-custom reconfigurable logic device design and implementation are time consuming processes. In this research, we propose a design framework in order to improve FPGA IP core design efficiency by link academic FPGA design flow and commercial VLSI CADs based on the synthesizable method. A novel FPGA routing tool is developed in this framework, namely the EasyRouter.

By using simple templates, EasyRouter can automatically generate the HDL codes and the configuration bitstream for an FPGA. With this design flow, accurate physical information can be reported when a new FPGA architecture is evaluated with reliable commercial VLSI CADs. For FPGA architectures that cannot be easily implemented with present

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Medium 9781601322623

On-demand Fault Scrubbing Using Adaptive Modular Redundancy

Toomas P. Plaks CSREA Press PDF

Int'l Conf. Reconfigurable Systems and Algorithms | ERSA'13 |

On-demand Fault Scrubbing Using Adaptive Modular Redundancy

Naveed Imran, Rizwan A. Ashraf, and Ronald F. DeMara

Department of Electrical Engineering and Computer Science

University of Central Florida, Orlando, FL 32816-2362, United States

Abstract— We present an architectural framework for NModular Redundant (NMR) systems exploiting the dynamic partial reconfiguration capability of FPGAs. Partial reconfiguration is used to dynamically construct the throughput datapath under failure conditions. The throughput datapath utilizes only one instance of a Functional Element (FE) while the other instances undergo evaluation by being subjected to the same actual inputs to the system. A software-based process is shown to be sufficient to periodically monitor the health of the active and standby FEs, thus avoiding a hardware voter in the datapath. The defective behavior of an active FE triggers the reconfiguration process and consequently a healthy element is introduced into the datapath.

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Medium 9781601322623

An Area-Efficient Asynchronous FPGA Architecture for Handshake-Component-Based Design

Toomas P. Plaks CSREA Press PDF

Int'l Conf. Reconfigurable Systems and Algorithms | ERSA'13 |

15

An Area-Efficient Asynchronous FPGA Architecture for

Handshake-Component-Based Design

Yoshiya Komatsu, Masanori Hariyama, and Michitaka Kameyama

Graduate School of Information Sciences, Tohoku University

Aoba 6-6-05, Aramaki, Aoba, Sendai, Miyagi, 980-8579, Japan

Abstract— This paper presents an area-efficient FPGA architecture for handshake-component-based design. The handshake-component-based design is suitable for largescale, complex asynchronous circuit because of its understandability. However, conventional FPGA architecture for handshake-component-based design is not area-efficient because of its complex logic blocks. This paper proposes an area-efficient FPGA architecture that combines complex logic blocks (LBs) and simple LBs. Complex LBs implement handshake components that implement data path controller, and simple LBs implement handshake component that implement data path. The FPGA based on the proposed architecture is implemented in a 65nm process. Its evaluation results show that the proposed FPGA can implement asynchronous circuits efficiently.

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