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Analog and Digital VLSI Circuit Design

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The book Analog and Digital VLSI Circuit Design is primarily intended as a comprehensive textbook at the senior level and first-year graduate level as well as a reference for practising engineers in the areas of integrated circuit design, digital design and VLSI. It is also helpful to practising engineers and scientists who wish to update their knowledge in the fast changing field of VLSI circuit design. Recognizing that the area of digital integrated circuit design is evolving at an increasingly faster pace, the author has made every possible effort to present up-to-date materials on all subjects covered. It contains the basics of silicon-based Very Large Scale Integrated (VLSI) system design topics and explains how they are required in many industries.

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CH1-1

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Chapter

1

INTRODUCTION TO

ASIC

1.1 INTRODUCTION

ASIC — Application Specific Integrated Circuits (ASICs) refer to those integrated circuits specifically built for specific tasks.

There are many advantages of ASICs as mentioned below :

• Increased speed

• Lower power consumption

• Lower cost (for mass production)

• Better design security (difficult reverse engineering)

• More compact board design (less complex PCB, less inventory costs).

However, there are some disadvantages :

• Long turnaround time from silicon vendors (several weeks)

• Expensive for low-volume production

• Very high NRE cost (high investment in CAD tools, workstations, and engineering manpower)

• Once committed to silicon the design cannot be changed.

1.2 STRUCTURED DESIGN

Over the years, a number of structured design techniques have been developed to deal with complex hardware and software projects. Not surprisingly, the techniques have a great deal of commonality. Design techniques are classified as hierarchy, modularity, and locality.

 

CH1-2

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INTRODUCTION

TO

ASIC

11

Fig. 1.12

1.9 LOOK-UP TABLES

The way logic functions are implemented in a FPGA is another key feature.

Logic blocks that carry out logical functions are look-up tables (LUTs), implemented as memory, or multiplexer and memory.

Figure 1.13 shows these aternatives, together with an example of memory contents for some basic operations.

A 2n – 1 ROM can implement any n-bit function. Typical sizes for n are 2, 3, 4 or 5.

In Fig. 1.13 (a), an n-bit LUT is implemented as a 2n – 1 memory; the input address selects one of 2n memory locations. The memory locations (latches) are normally loaded with values from user’s configuration bit-stream.

In Fig. 1.13 (b), the multiplexer control inputs are the LUT inputs. The result is a generalpurpose “logic gate.” An n-LUT can implement any n-bit function. An n-LUT is a direct implementation of a function truth table.

Each latch location holds the value of the function corresponding to one input combination.

(a)

(b)

(c)

Fig. 1.13. Look-up table implemented as (a) memory or (b) multiplexer and memory

 

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ASIC DESIGN RULES

23

2.1.7 Polysilicon Deposition and Patterning

2.1.8

A layer of polysilicon is deposited over the entire wafer surface

The polysilicon is then patterned by a lithography sequence

All the MOSFET gates are defined in a single step

The polysilicon gate can be doped (n+) while is being deposited to lower its parasitic resistance (important in high speed fine line processes)

PMOS Formation

— Photoresist is patterned to cover all but the p+ regions

— A boron ion beam creates the p+ source and drain regions

— The polysilicon serves as a mask to the underlying channel

• This is called a self-aligned process

• It allows precise placement of the source and drain regions

— During this process the gate gets doped with p-type impurities

• Since the gate had been doped n-type during deposition, the final type (n or p) will depend on which dopant is dominant

2.1.9

NMOS Formation

— Photoresist is patterned to define the n+ regions

— Donors (arsenic or phosphorous) are ion-implanted to dope the n+ source and drain regions

 

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ANALOG

AND

DIGITAL VLSI CIRCUIT DESIGN

Poly contact (CCP)

Active contact (CCA)

5.1(a)

exact contact size

2×2

5.2(a)

minimum poly overlap

1.5

5.3(a)

minimum contact spacing

2

6.1(a)

exact contact size

2×2

6.2(a)

minimum active overlap

1.5

6.3(a)

minimum contact spacing

2

6.4(a)

minimum space to gate of transistor

2

1. To ensure source and drain width.

2. Different select types may touch but not overlap.

• MOSIS Scalable CMOS rules — Process back end:

Layer

Rule

Explanation

Value/λ

λ

Metal 1 (CMF)

7.1

minimum width

3

7.2(a)

minimum space

3

7.2(b)

minimum space (for minimum-width wires

Via 1 (CVA)

Metal 2 (CMS)

Via 2 (CVS)

Metal 3 (CMT)

only)

2

7.3

minimum overlap of poly contact

1

7.4

minimum overlap of active contact

1

8.1

exact size

2×2

8.2

minimum via spacing

3

8.3

minimum overlap by metal 1

1

8.4

minimum spacing to contact

2

8.5

minimum spacing to poly or active edge

2

9.1

minimum width

3

9.2(a)

minimum space

4

9.2(b)

minimum space (for minimum-width wires only)

3

9.3

minimum overlap of via 1

1

14.1

exact size

2×2

14.2

minimum spacing

3

14.3

minimum overlap by metal 2

1

 

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ANALOG

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DIGITAL VLSI CIRCUIT DESIGN

node. Similarly, a logic ‘0’ output will result from a logic ‘1’ input. The nMOS transistor connected in the bottom realizes this when its gate is given a logic ‘1’ input and its source is connected to logic

‘0’ or ground (VSS). In this case, the nMOS transistor channel acts like a wire resulting in logic

‘0’ at the output while the pMOS transistor channel is simply devoid of any conductive channel.

The inverter can best be considered as the central part of digital designs. A thorough understanding of its operation and properties is required to design more complex structures like NAND and NOR gates, adders and multipliers.

3.2 RESISTIVE LOAD INVERTER

The MOSFET is used in enhancement type nMOS and the input is applied to the gate of the nMOS transistor which is also known as driver.

The load is a simple linear resistor R which is connected between the drain and the supply voltage VDD. The substrate of the driver is grounded and the source is also kept at a ground potential. Since VSB = 0, the threshold voltage of the driver is VTO (VT at VSB = 0).

 

CH3-2

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INVERTER

47

Propagation Delay, Noise Margin, Rise Time and Fall Time :

τPHL =

K M1

  VDD – VtM2

 1

τ

− 1  + 

 ln  4

(– VtM1 )   VDD + VOL

 2 

Fig. 3.10

τPLH =

K M1

C

(− VtM1 )

   – VtM1 

VDD + VtM1 – VOL 

ln 4 

.

 − 1 + 2

– VtM1



   VDD – VOL 



Rise Time : tr =

K M1

C

(− VtM1 )

   20 VtM

1

ln   −

∆V

  

VDD + VtM1 – VOL – 0.10 V 

 − 1 + 2

(− VtM1 )





Fall Time : tf =

C

K M2 (VDD

   VDD + VtM 

VtM2 – 0.1 ∆V 

2

 − 1 + 2

ln  2 

VDD − VtM2 ) 

– VtM2 )    VDD – 0.9 ∆V 



Noise Margin :

NMH = VOH – VIH

NML = VIL – VOL.

3.4 CMOS INVERTER

The CMOS inverter consists of an enhancement type nMOS and an enhancement-type pMOS transistor, operating in complementary mode. This configuration is called complementary

MOS (CMOS).

The circuit topology is complementary purple-pull in the same that for high input, the nMOS transistor drives (pull down) the output mode while the p-MOS transistor acts as the load, and for low input the p-MOS transistor drives (pull-up) the output node while the nMOS transistor acts as the load.

 

CH4-1

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Chapter

4

STATIC VLSI DESIGN

4.1 INTRODUCTION

There are numerous circuit styles to implement a given logic function. As with the inverter, the common design metrics by which a gate is evaluated are area, speed, energy and power.

Depending on the application, the emphasis will be on different metrics, by which a gate is evaluated. For example, the switching speed of digital circuits is the primary metric in a high performance processor, while in a battery operated circuit, it is energy dissipation.

Recently, power dissipation also has become an important concern and considerable emphasis is placed on understanding the sources of power and approaches to dealing with power. In addition to there metrics, roburtness to noise and reliability are also very important considerations.

The complementary CMOS circuit style falls under a broad class of logic circuits called static circuits in which at every point in time, each gate output is connected to either VDD or VSS via a low resistance path.

There are different static design procedure exist in VLSI circuit design technology:

 

CH5-1

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Chapter

5

DYNAMIC VLSI DESIGN

5.1 INTRODUCTION

In the static CMOS logic with a fan-in of N requires 2N devices. A variety of approaches were presented to reduce the number of transistors required to implement a given logic function including pseudo-nMOS, pass-transistor logic. etc. For the pseudo, nMOS logic, there are (N + 1) no of transistor required to implement an N input logic gate, but it has static power dissipation.

To avoid this static power dissipation and obtaining the same result, the alternating approach is called the dynamic logic design. With the addition of a clock input, it uses a sequence of precharge and conditional evaluation phase.

There are different style to design a dynamic VLSI circuits:

(i) Precharge evaluation logic style.

(ii) Dynamic TG logic style.

(iii) Pass transistor logic style.

(iv) Domino logic style.

(v) NORA logic style.

5.2 PRE-CHARGE AND EVALUATION LOGIC STYLE

The operation of this circuit is divided into two major phases — pre-charge and evaluation — with the mode of operation determined by the clk signal clk. The basic construction of this type of design style is given below.

 

CH6-1

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Chapter

6

SEQUENTIAL LOGIC CIRCUIT

DESIGN

6.1 INTRODUCTION

If we neglect the propagation delay time, the output of the combinational logic circuit, at any given time point are directly determined as Boolean function of the input variables applied at that time. Thus, the combinational circuits lack of the capability of storing any previous events, or displaying an output behaviour which is dependent upon the previously applied inputs.

The sequential circuit gives the output, which is determined by the current inputs as well as the previously applied input variables.

Bistable circuits have, as their name implies, two stable stages or operation modes, each of which can be attained under certain input and output condition.

Monostable circuits, have only one stable operating point (state).

All basic Latch and flip-flop circuits, registers and memory elements used in digital systems fall into this category.

6.2 BEHAVIOUR OF BI-STABLE ELEMENTS

The basics of a bi-stable elements is that, it has two identical cross-coupled inverter circuits, as shown in figure given below:

 

CH7-1

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Chapter

7

ARITHMETIC SUBSYSTEM

7.1 CARRY LOOKAHEAD ADDER

The linear growth of adder carry delay with the size of the input word may be improved by calculating the carries to each stage in parallel.

The carry of the ith stage, Ci may be expressed as,

Ci = Gi + Pi . Ci – 1 where

...(i)

Gi = Ai . Bi

generate signal

Pi = Ai ⊕ Bi

propagate signal

...(ii)

...(iii)

Expanding this, we get,

Ci = Gi + Pi Gi – 1 + Pi Pi – 1 Gi – 2 + ....... + Pi Pi – 1 ...... P1 C0

...(iv)

The sum Si is generated by

Si = Ci – 1 ⊕ Ai ⊕ Bi if

...(v)

Pi = Ai ⊕ Bi

For four stages of lookahead, the appropriate terms are

C1 = G1 + P1C0

C2 = G2 + P2G1 + P2P1C0

C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0

C4 = G4 + P4G3 + P4P3G2 + P4P3P2G1 + P4P3P2P1C0

= G4 + P4 [G3 + P3{G2 + P2(G1 + P1C0)}]

...(vi)

A possible implementation of the carry gate for this kind of carry lookahead adder for

4 bits is shown in Fig. 7.1(a). Note that the gates have been partitioning to keep the number of inputs less than or equal to four. This is typical of the type of carry lookahead that would be used in a gate array or standard cell design.

 

CH7-2

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ARITHMETIC SUBSYSTEM

93

Read 1:

(i) After the write ‘1’ operation is completed, the write access transistor M1 is turned off.

(ii) With the storage capacitance C1 charged upto a logic high level, transistor M2 is now conducting.

(iii) ‘Read select’ signal RS must be pulled high during the active phase of φ2 following a precharge cycle.

(iv) Read access transistor M3 turns ON, M3 and M2 create a conducting path between the data read column capacitance C3 and ground.

(v) The capacitance C3 discharges through M2 and M3 and the falling column voltage is interpreted by the ‘data read’ circuitry as a stored logic ‘1’.

Fig. 7.10

7.5 READ ONLY MEMORY

It is a permanent or semi-permanent memory. In permanent ROM, the data is permanently stored and cannot be changed. It can only be read from the memory. There cannot be a write operation because the specified data is programmed into the device by the manufacturer or user. In semi-permanent ROM also there is no write operation, but the data can be altered by special method.

 

CH8-1

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Chapter

8

FLOORPLANNING,

PLACEMENT, PARTITIONING

AND ROUTING

8.1 FLOORPLANNING

Floorplanning is the art of any physical design.

A well thought-out floorplan leads to an ASIC design with higher performance and optimum area.

Floorplanning can be challenging in that it deals with the placement of I/O pads and macros as well as power and ground structures.

Before one proceeds with physical floorplanning one needs to make sure that the data used during the course of physical design activity is prepared properly.

Proper data preparation is essential to all ASIC physical designs in order to implement a correct-by-construction design.

The types of data that are required to start a physical design are:

• Related technology and library files

• Circuit description of the design in the form of netlist representation

• Timing requirements or design constraints

• Floorplan

8.2 TECHNOLOGY FILE

Technology files contain information or commands that are used to configure structures, parameters (such as physical design rules and parasitic extractions), and limits of an ASIC design targeted to specific process technology.

 

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Fig. 8.3. Ring and Core Power and Ground

As the ASIC core power consumption (dynamic and static) increases, the distance of power and ground strip intervals increases. This increase in the power and ground strip intervals is used mainly to reduce overall ASIC voltage drop, thereby improving ASIC design performance.

In addition to the core power and ground ring, macro power and ground rings need to be created using proper vertical and horizontal metal layers. A macro ring encloses one or more macros, completely or partially, with one or more sets of power and ground rings.

Another important consideration is that when both analog and digital blocks are present in an ASIC design, there is a need for special care to insure that there is no noise injection from digital blocks or core into the sensitive circuits of analog blocks through power and ground supply connections.

The most effective method is to decouple the digital and analog power and ground by routing the digital power/ground (DP and DG) and analog power/ground (AP and AG) supply connections separately as shown in Fig. 8.4.

 

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DIGITAL VLSI CIRCUIT DESIGN

• D′′x = D′x + 2cxp – 2cxq, ∀ x ∈ A – {p}

D′′a = D′a + 2cac – 2cae = 0 + 2 × 2 – 2 × 2 = 0

D′′d = D′d + 2cde – 2cdc = 1 + 2 × 4 – 2 × 3 = 3

• gxy = D′′x + D′′y – 2cxy

g3 = – 3) gad = D′′a + D′′d – 2cad = 0 + 3 – 2 × 3 = – 3 ( ¶ n gi = 0 ).

• Note that this step is redundant ( ∑ i = 1 µ

¶ = g = – 3. g1 = gbf = 4, ¶ g2 = gce = – 1, g

• Summary ¶

3 ad

• Largest partial sum max

k

∑i=1

µ gi = 4 (k = 1)

⇒ Swap b and f.

Weighted Example (cont’d) a b c d e f

a

b

c

d

e

f

0

1

2

3

2

4

1

0

1

4

2

1

2

1

0

3

2

1

3

4

3

0

4

3

2

2

2

4

0

2

4

1

1

3

2

0

Initial cut cost = (1 + 3 + 2) + (1 + 3 + 2) + (1 + 3 + 2) = 18(22 – 4)

• Iteration 2 : Repeat what we did at Iteration 1 (Initial cost = 22 – 4 = 18).

¶ = g = 4. g1 = gce = – 1, ¶ g2 = gab = – 3, g

• Summary : ¶

3 fd

• Largest partial sum = max

∑i=1 k

µ gi = 0 (k = 3)

⇒ Stop !

Algorithm : Kernighan-Lin (G)

Input : G = (V, E), | V | = 2n.

Output : Balanced bi-partition A and B with “small” cut cost.

1. begin

2. Bipartition G into A and B such that | VA | = | VB |, VA ∩ VB = φ, and VA ∪ VB = V.

 

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DIGITAL VLSI CIRCUIT DESIGN

8.21 DETAIL PLACEMENT

A detail placement algorithm is executed to refine their placement based on congestion, timing and power requirements. Congestion refinement or congestion driven placement is more beneficial ASIC designs with very high density and the objective of the detail placer is to distance standard cell instances from each other such as more routing tracks are created among them.

Timing driven placement algorithm is classified as either

– net based or

– path based algorithm

Net based schemes try to control the delay on a signal path by imposing an upper bound delay.

Path based approaches apply the constraints to the delay paths of small sub-circuits.

The most commonly used algorithm used for the detail placement is simulated annealing.

8.21.1 Simulated Annealing

It is a simulation based placement technique. It is used as an iterative improvement algorithm during detail placement algorithm. The objective of this procedure is to find an optimal or near optimal placement for each pre-placed standard cell instances.

 

ch9-1

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Chapter

ANALOG VLSI DESIGN

9

9.1 MOS AS A SWITCH

MOS transistor that is to be used as a switch.

A or B, can be the drain or the source of the MOS transistor depending on the terminal voltages (e.g., for an n-channel transistor, if terminal A is at a higher potential than B, then terminal A is the drain and B is the source terminal). The ‘ON’ resistance consists of the series combination of r0, rS and whatever channel resistance exists.

Typically by design, the contribution from rD and rS is small such that the primary consideration is the channel resistant.

Fig. 9.1(a)

In the ‘ON’ state of the switch the voltage across the switch should be small and Vas should be large. Therefore, the MOS device is assumed to be in the non-saturation region we know, iD =

k′W

L

V 2

(VGs − VT ) VDS − DS  where 0 < VDS < VGs – VT

2 



(VGs becomes VGD if VDS is negative).

The small signal channel resistance is given as,

rON =

1

δI D

δVDS

=

Q

1 k′W

(VGs − VT − VDS )

L

✰ rON is 2 to 3 times low for n-type than p-type so, n-type switch is preferable over p-type.

 

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DIGITAL VLSI CIRCUIT DESIGN

2ID1

2ID2

vin1 – vin2 = (vgs1 = vgs2) =

or,

(vin1 – vin2)2 =

or,

1

W

K′

(vin1 – vin2)2 – ISS = – 2 ID1 ID2

2

L

or,

4ID1ID2 = (ID1 + ID2)2 – (ID1 – ID2)2

or,

K′

W

L

K′

(when, VT1 = VT2 = VT)

W

L

2

(I – 2 ID1 ID2 )

W SS

K′

L

(...

ID1 + ID2 = ISS)

...(1)

4ID1ID2 = ISS2 – (ID1 – ID2)2

...(2)

Again, from equation (1),

2

4ID1ID2 = ISS2 +

W

1 

1

W

4

I (v – vin2)2

 K ′ L  (vin1 – vin2) – 2. K′

4 

2

L SS in1

Equating equation (2) and equation (3), we get,

2

K′W

 K′ W 

ISS2 – (ID1 – ID2)2 = ISS2 + 

(vin1 – vin2)4 –

ISS (vin1 – vin2)

L

 2 L

or,

1

(ID1 + ID2) = –

4

Thus,

(ID1 + ID2)2 =

2

2

W

 K ′ W

4

2

 K ′ L  (vin1 – vin2) + ISS 

 (vin1 – vin2) .

 L 

1

W

µ c

(vin1 – vin2)

2 n ox L

4ISS

µ n cox

where K′ = µn cox.

If, vin1 = vin2 then ID1 – ID2 = 0 or ID1 = ID2.

W

L

− (vin1 – v in2 ) 2

As |vin1 – vin2| increases from zero, then |ID1 – ID2| also increases.

* ∴ Gm =

δ(∆ID )

1

W

=

µn cox

2

L

δ(∆Vin )

For, ∆Vin = 0,

Since,

Gm =

µn cox

4ISS

2

− 2∆Vin

µn cox W/L

4ISS

2

− ∆Vin

µ n cox W/L

W

I

L SS

Vout1 – Vout2 = ∆I . RD = RD Gm . ∆vin

Av =

µn cox

 

ch10-1

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ANALOG

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DIGITAL VLSI CIRCUIT DESIGN

10.2 SWITCHED CAPACITOR INTEGRATOR

A : Continuous Time Integrator : Very important component of filters and over sampled A/D converters, is the continuous time integrator. Figure 10.3 shows the circuit.

The output is,

Vout = –

1

R cf

|Vin dt

...(4)

Fig. 10.3

(if the output Amp. gain is very large).

For sampled data system, we need a discrete-time counterpart of this circuit.

B : Discrete Time Integrator :

Here, we replace r by a switched capacitor.

Fig. 10.4. Response to a constant input voltage

Z1 =

1

1

. Z2 = j ωc1 j ωc2

Vout = –

Z2 jωc1

1

V =–

.

Vin = –

Z1 in

1 jωc2

c1 c2

Vin

Operation : In every clk pulse,

(1) When S1 is ‘ON’ ; c1 absorbs a charge c1 Vin.

(2) When S2 is ‘ON’

Deposite this charge on c2.

(... Op-Amp. input does not draw any current).

 c1 

Therefore, if Vin is constant, the output changes by   Vin/clock cycle.

 c2 

The output waveform is a staircase function. If we can approximate this staircase by a ramp, we get an integrator [c2 must be large capacitor.]

The output at the end of the kth clock cycle is,

 

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